)
with energies of 40 and 30 MeV, emitted in the same direction, can produce a
70 MeV-like signal in a crystal. The efficiency of identifying such pulses
depends on the double-pulse spatial and timing resolution of the detector. For detailed evaluation of pile-up pulses from fast detectors, digitization of the signals has become essential in many modern detector systems. The analog waveforms of the detector signals are captured as "snap shots", i.e. sampled at a high frequency (500-800 MHz) for a limited period of time, and the samples are stored in an analog memory. The analog samples are then retrieved at a lower rate and digitized with an ADC before a new waveform is acquired. Many digitizers may be multiplexed onto one ADC module. However, in order to maximize the readout speed and reduce the amount of data, implementation of zero suppression is of high importance for the successful use of such devices. An example of a fast digitizing system is the 1024 channel transient digitizer system consisting of 128-bin GaAs CCDs [Dav 93], [Bry 91].
A different waveform digitizing system is being developed at PSI and will be implemented in the pion beta experiment: The Domino Sampling Chip (DSC), a fast analog memory fabricated in CMOS technology. It is a waveform sampling device based on a switched capacitor architecture. A first prototype consisting of 32 bins was designed by R. Horisberger (PSI) in 1989 [Bro 90], [Gol 93]. A second and third enlarged version of the chip with 192 bins, were tested in 1993 and gave satisfactory response to different waveforms [Broe 94]. The yield of properly operating chips, however, was very low. The performance of the forth iteration, a 128-bin device, is the subject of this chapter. The principle of operation of the DSC is explained and the design of a motherboard, hosting a number of DSCs is elaborated. The dynamic behavior of a waveform digitizing system consisting of six DSC channels (i.e. six DSCs with each 128 bins) is presented.