7.4 Summary and Discussion
A summary of the performance of the DSC V4 is given in table 7.1. The quoted
values should be interpreted as upper limits, since they are the maximum values
of a sample of 6 DSCs. In addition, the values for non-linearities include the
corresponding non-linearities of the FB ADC's and TDC's.
Figure
7.13:
Top: Signal from a CsI crystal sampled with a DSC after pedestal subtraction,
smoothing and conversion to a two nanosecond time base. The main parameters of
the pulse such as rise-time and fall-time are the same as displayed in Fig 5.3.
Bottom: DSC integral plotted against the FB ADC value for 3000 events of a run
with cosmic muons.
It should be mentioned here that the data were taken under realistic
experimental conditions:
1. The read out of the DSCs and the A/D conversion was done at rate of
2.5 MHz
2. The tests were performed in an "experimental" environment, i.e. in a fully
equipped counting house.
The results are very promising: The DSC V4 can be used with a board similar to
that of the DSM100. With the present lay-out of the chip and the number of
necessary connections, it is possible to obtain a density of 16 DSCs per
NIM-module. With 64 DSC channels on 4 NIM-boards (250 SFr each) connected to 1
ADC (4000 SFr.), the costs would be about 80 SFr/channel. The equipment for the
250 CsI crystals with DSCs for the pion beta experiment would be feasible with
the present version and would cost about 20000 SFr. However, an even higher
density of DSCs in a single NIM module would be desirable, in order to lower
the costs per channel.
Input
range
|
±0.8
V
|
Minimum
sampling frequency
|
100
MHz
|
Maximum
sampling frequency
|
800
MHz
|
Noise
(rms)
|
2.0
mV
|
Pedestal
variation (max)
|
±10
mV
|
Precision
of sampling-speed calibration
|
<0.2%
|
Temperature
coefficient of sampling frequency
|
(-2.7±0.1)°/oo/°C
|
Timing
non-linearity
|
<±0.3
ns (max)
|
Timing
resolution
|
<0.2
ns (rms)
|
Amplitude
non-linearity
|
<±1.3
mV (max)
|
Table
7.1:
DSC performance under experimental conditions. The values for timing resolution
and non-linearity are relative to FASTBUS ADC's and TDC's.
There are publications about prototypes of similar switched capacitors chip
architectures [Hal 94]. This chip consists of 32 bins and has been tested under
laboratory conditions with a 16 bit ADC at a readout frequency of
~0.09 MHz. The quoted result for rms noise is a factor of 7 lower than the
value in table 7.1. This indicates, that the presented results are not only
features of the DSC itself, but rather represent the performance of a complete
waveform digitizing system operated under experimental condition.