Checking trigger timing

The trigger timing is essential for the experiment and needs to be checked whenever something gets changed in the trigger logic, like the prescaling factors in the LB 500 Prescaler. Following table gives the signals to check.

Example signals were taken on August 2nd, 1999, at 160k PiStop rate. Channel one sees Signal1, channel 2 sees Signal 2. All times are Full Width Tenth Maximum.

Item	Signal 1	Signal 2	Comment	Example
1	Pi-Beta Hi	CsI Hi	Width 8.5-9ns Trailing edges aligned
2	Pi-Beta Lo	CsI Lo	Width 8.5-9ns Jitter larger than for Hi signals
2.5	beam	Pi-Beta Lo	Pibeta Lo stops ~1ns before beam
note	all above four triggers should be compared with beam veto
3	Beam	CsI Hi	Beam Width 15ns CsI Hi starts ~3ns after beam and stops ~1ns before beam
4	Pi-Stop	CsI Hi	Pi-Stop width 8.5-9ns CsI Hi starts ~2ns after Pi-Stop
5	CsI Hi Pi-Beta Hi	CsI Lo Pi-Beta Lo	Lo and Hi signals aligned trailing edge Same width as Hi
6	Three	Beam Veto	Tigger three is well contained inside the beam veto.
7	Pi-Stop PS Pi-Beam	Pi-Stop	Pi-Stop PS width 9.5ns Pi-Beam width 13ns Trailing edges aligned if possible
8	Pi-Stop	Pi-Gate	Pi-Gate width 180ns Pi-Gate opens 30ns before Pi-Stop
9	Pi-Gate	Pi-Gate PS(Hi,PB,Lo)	Prescaled gates same timing as unprescaled one
10	Sum PV	CsI Hi	Width 20ns PV Starts ~7ns before CsI Hi
11	CMV	Pi-Beta Hi	CMV width 60ns CMV comes ~23ns before Pi-Beta Hi
12	CMV PS	CMV	CMV PS Width 44ns CMV PS comes 6ns after CMV
13	Random		Width 25ns
14	Any CsI at splitter output	FB ADC gate at fan-out	Gate width 100ns CsI signal comes 52ns after gate
15	Any BADC input switch trigger to prompt (16)	BADC gate	Gate width 25ns beam signal comes 2ns after gate due to internal delay in LRS2248
16	e+ Beam switch trigger to eBeam (256)		eBeam trigger width 9ns Timed only at BADC (CAMAC) B0/B1 comes 10ns after gate others come 2ns after gate