7.2.3 THE MOTHERBOARD DSM100
The DSM100 hosts a number of DSCs. In the present version, it is a NIM-module
equipped with 8 DSC channels. The main features of the DSM100 are as follows:
* Power supply and generating of the control signals for the DSCs.
* Triggering of the DSCs by a common GATE pulse
* Serial read-out of the DSCs, initiated by the START pulse.
* Supporting of the ZS mechanism, which can be enabled or disabled via the E_ZS
input.
* A common TEST input for all DSCs for calibration purposes.
Fig 7.4 shows a schematic layout of the DSM100. The logic signals provided to
the DSCs are TTL signals shifted to "0"=-1.5V and "1"=3.5V.
The dynamic input range of the DSC is about ±0.8 V. The analog OUT and
the CONVERT signal of the DSM100 are supplied to the converter module SIROCCO
III. The SIROCCO III is a 10Bit FADC residing in CAMAC, which converts the
analog data and stores the digitized information in its internal buffer of 8kB.
This buffer can be accessed via CAMAC with simple read statements.
Figure
7.4:
Schematic layout of the DSM100[16],
where the interconnection of the zero suppression part (DSC ZS) to the sampling
and readout part (DSC SP) is indicated. The eight analog signals to be sampled
are supplied to IN 1...IN 8. The outputs of the DSCs are connected to the
output amplifier and then transmitted to the ADC. The CONVERT-signal
synchronizes the conversion of the analog signal in the ADC. The encoding
mechanism is necessary if zero suppression is enabled with the signal E_ZS: the
status lines A1 to A4 correspond to the DSC number currently read out and are
fed into the ADC. The analog level of the ZS comparator (Fig. 7.3) is common
for all DSCs and supplied via the TRESH input.
The output amplification is chosen such as to match the input range of the
SIROCCO III, which is ±2.5 V. The resulting ADC-values are converted to
the input signal amplitude in mV using
1 ADC count = 1 mV. (7.1)
[16] The DSM100 was developed by R. Schnyder (PSI).