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First and Second Level Pedestal Corrections

  The pedestal value of the ADC output is an effective offset. It is defined by the integration of the excess signal from the gate pulse which allows current to pass into the ADC. In order to correct for this offset, the pedestal values are measured and recorded periodically during data acquisition for each ADC channel. This is done by using a clock as the trigger, which avoids the acceptance of data signals from the various detectors. Then, during the data replay, these pedestals are subtracted from their respective ADC channels, on an event by event basis.

Following the first (absolute) pedestal subtraction, a second pedestal subtraction algorithm is implemented to remove low energy common mode noise from the data. The second pedestal subtraction algorithm works as follows:

Figure 4.1 depicts a typical pedestal spectrum, before and after the second pedestal subtraction algorithm. One can see that noise level decreases from tex2html_wrap_inline534440 channels (1.6 MeV) to about 5 channels (0.2 MeV).

  figure1163
Figure 4.1: CsI Pedestal spectra before and after second pedestal subtraction algorithm has been implemented.

Figure 4.2 shows the 44 CsI pedestal spectra, after the first and second pedestal subtraction have been implemented.

  figure1171
Figure 4.2: Final CsI pedestal spectra after both first and second pedestal corrections, viewed from two different angles.

By inspection of this histogram, one can see that a summing threshold of tex2html_wrap_inline5346 channels (0.2 MeV) can be chosen to separate noise from data. All CsI ADC values which are below tex2html_wrap_inline5348 are considered to be noise and are ignored, while all that are above tex2html_wrap_inline5348 are summed as data.

The first and second pedestal subtraction algorithms are also applied to the 64-element NaI array, after which one can safely select tex2html_wrap_inline5352 channels (0.4 MeV). Figure 4.3 shows the 64 NaI pedestal spectra after the first and second pedestal subtractions. This discrepancy between tex2html_wrap_inline5348 and tex2html_wrap_inline5356 is due to the fact that the ADC gate width for the NaI detectors was longer (800 ns) than that of the CsI detectors (100 ns). Hence, more low energy noise was integrated by the ADC for the NaI channels.

  figure1185
Figure 4.3: Final NaI pedestal spectra after first and second pedestal corrections, viewed from two different angles.

Finally, one can see the root mean square values for the corrected CsI and NaI pedestal histograms in Fig. 4.4. The root mean square value tex2html_wrap_inline5358 is calculated as
equation1195
where tex2html_wrap_inline5360 is the ADC value of the ith bin in the pedestal histogram, tex2html_wrap_inline5084 is the mean, and N is the total number of events.

  figure1201
Figure 4.4: Root mean square tex2html_wrap_inline5358 values of the corrected CsI and NaI ADC pedestal histograms.


next up previous contents
Next: Gain Matching Up: Energy Calibration of Pure Previous: Energy Calibration of Pure

Penny Slocum
Fri Apr 2 00:36:38 EST 1999