The DSC Controller

The DSC system consists of three components which are connected via a backplane bus: The Power Module provides the DSC system power. It gives out the necessary +/- 5V, -1.5V and +3.5V. The DSC Controller or DSC Sequencer receives the steering signals from the experiment as GATE, RESET, START Convert and Testpulse.
It gives out the Flash ADC GATE and the Flash ADC Converts as the DSC control signals /Busy, Read Bit In (RBI), Clear, Enable Zero Suppression (EnZS), the Readout Phase clocks Phi 1 and Phi 2, GATE and the Testpulse.
The main part of the DSC Sequencer is an Altera epm7032s FPGA which produces all control signals from the input signals.

The necessary input signals for the DSC Controller and their timing:

The first necessary signal is the GATE which is a NIM pulse. This signal has to be timed in with the analog pulse which has to be sampled. The internal time delay of the GATE signal is ~30 ns. So the analog signal has to be set that it comes ~30 ns after the GATE. The signal length is ~150 ns. This pulse is taken as early as possible from the master coincidence, defining a trigger. The other control signals are generated delayed from this signal.

The START Convert is a TTL signal which should come about 300 ns after the GATE is off. The length is not critical and should be ~200 ns wide. It starts the Readout phase of the chip, starts teh whole re-read procedure by internal signals and also starts output of the FADC control signals.

The TTL Testpulse should also be correlated with the GATE signal. At least it should be 50 ns delayed after the GATE. The length depends on the chosen Domino Speed and is 100 ns in the Experiment, but it might be that the time difference between the timing peaks is different, because there are TTL drivers and a Schmitt Trigger inbetween to refresh the TP signal which comes into the modules via backplane bus, which may change the Testpulse length.

The output signals on the frontside of the Controller are the ADC Trigger signal and the ADC Clock convert pulses. These convert pulses have to be timed in relative to the DSC Analog Output which contains the data to be converted. These signals are TTL standard. The timing shoul look like:

Links:

The DSC in the PIBETA Experiment

Layout of the multilayer motherboard and DSC carrier. Pictures and PS-Downloads

Return to the DSC Main Page

.